Semiconductor packages including a semiconductor chip mounted on a substrate suffer from the problem of crack formation at the interfaces between the different materials of the package. Conventional methods for attaching semiconductor chips to a substrate, such as a die pad, include gluing, soldering and alloying. A newer attachment technique is diffusion soldering. Compared to the other methods, diffusion soldering provides a higher mechanical robustness and better thermal performance. Based on the higher mechanical stability of the die attachment, diffusion soldered units show improved behaviour regarding solder crack and fatigue. However, thermal contraction can cause cracks in the silicon in devices processed with diffusion soldering. During thermal cycling of the component, stress occurs at the interfaces due to the difference in the thermal expansion coefficients between the different materials, for example between the die pad of a metal leadframe and a semiconductor chip. This stress can lead to the formation of cracks and even to complete delamination of the chip from the die pad.
Thermal mismatch is a problem for semiconductor chips that are mounted on a metal substrate by diffusion soldering. In these packages, the semiconductor chips are electrically connected to the metal substrate by the bond between the rear surface of the chip and the substrate. A diffusion solder bond has the advantage that a thin bond structure, for example around 10 μm, is provided. This improves thermal dissipation as well as enabling the size of the package to be reduced. However, as the bond structure is thin, it is less able to absorb the stress which occurs due to the mismatch in thermal expansion coefficients. Thermal mismatch is also a problem for other metallic chip interconnect techniques.
It is known to position a buffer layer directly on the rear side of the semiconductor chip or the front side of a die pad. The buffer layer is typically a ductile metal layer that absorbs stress and thereby mechanically decouples the semiconductor chip and the die pad. Existing applications use full-area metal plating (e.g. Ag, Ni/NiP, Au) for the buffer layer. In these applications, the buffer layer extends across the entire bottom surface of the semiconductor chip. By using die pad plating, the occurrence of silicon cracks is reduced, as the plating metal is more ductile than the copper base material of the die pad. However, a disadvantage of plating metals, such as Ag, Ni/NiP, and Au is their poor wettability and solderability compared to copper surfaces. The interdiffusion and intermetallic phase formation with the tin containing solder alloys (typically used in diffusion soldering) is lower for these plating metals than for copper.
For applications in which it is desirable to have a full-area void-free die attachment with appropriate thermal and electrical conductivity, bare copper die pads without plating are used. Since there is no buffering plating used in these applications, chip thickness and chip size are limited in order to prevent horizontal cracks in the silicon.